1. Field of the Invention
The present invention relates to an apparatus and a method for testing a memory device.
2. Description of the Related Art
A typical memory device includes a plurality of memory cells, each memory cell to store data. To access the data stored in a memory cell, the memory device receives an address of the memory cell, and provides the stored data corresponding to the address after a time delay, or latency. The duration of the latency may be controlled by a mode register set (MRS).
An electric die sorting (EDS) process may be used to test memory cells of the memory device. When a faulty cell is found during the EDS process, a redundancy algorithm is applied to the memory device so that the faulty cell is replaced with a redundancy cell. The redundancy algorithm is capable of recognizing the address of the faulty cell and replacing the memory cell located at the address with the redundancy cell. Faulty cells are typically replaced by cutting or maintaining a fuse. To correctly test faulty cells during the EDS process the address of the faulty cell should be correctly recognized.
FIG. 1 is a block diagram illustrating a conventional memory test device. Referring to FIG. 1, the memory test device includes an address generator 100, a data generator 110, a timing generator 122, and a failure discriminator 120. The address generator 100 receives an address generating command from a pattern generator (not shown). The address generator 100 includes a register 102, an Arithmetic and Logic Unit/Multiplexer (ALU/MUX) 104 and an address counter 106 to generate an address of a memory cell to be tested. The address counter 106 provides the address to the data generator 110.
The data generator 110 generates data to be written to the memory device under test (DUT) 124 according to the address and provides the data and address to an address/data bus 115. The data generator 110 includes a memory data generator 112 and an address scrambler 114. The memory data generator 112 generates the data to be written into the DUT 124. The address scrambler 114 may be used in some testing modes to replace the address with another address (not shown) provided external to the memory test device, and the address or the replaced address to the address/data bus 115.
Timing generator 122 receives the address and optionally the data from the data generator 110, and operation commands for controlling the operation of the DUT 124, over the address/data bus 115. The timing generator 122 provides the address and command(s) to the DUT 124, causing the DUT 124 to provide data stored in a memory cell corresponding to the address to the failure discriminator 120.
The failure discriminator 120 compares the data from the DUT 124 with an expected value and stores a comparison result for failure analysis and the redundancy algorithm. The comparison result indicates whether a memory cell of the DUT 124 is faulty. The failure discriminator 120 includes a comparator 126 and a failure memory 128.
The comparator 126 receives and compares the data from the DUT 124 and the expected value, and stores the result of the comparison in the failure memory 128 according to the address from the data generator 110 carried on the address/data bus 115. However, since the retrieval of stored data from the DUT 124 has a delay, in a high-speed test operation, the address provided to the failure memory 128 may not be the same address used to access the DUT 124. Consequentially, a faulty memory cell may be undetected, and a correctly operating memory cell may be mistakenly replaced.
FIG. 2 is a timing diagram illustrating operation of the conventional memory test device shown in FIG. 1. Referring to FIG. 2, a memory command is generated in response to an input clock signal having a predetermined frequency. A row active command ACT is detected at a rising edge of the input clock, and activates a word line of a memory cell array of the DUT 124. When the row active command ACT is detected, an address applied to the DUT 124 is identified as a row address, and a word line corresponding to the identified row address is activated. When a read command RD is detected at the rising edge of the input clock, a corresponding bit line of the DUT 124 is electrically connected to a local data line, allowing the data stored on the bit line to pass through internal functioning blocks (not shown) of the DUT 124. In other words, when a row address and a column address are provided to the DUT 124, the data stored in the memory cell corresponding intersection of the row and column addresses are provided to the failure discriminator 120 after predetermined number of clock cycles, or latency.
At internal clock periods CK5 and CK6, data stored in a memory cell corresponding to a row address X1 and a column address Y1 is provided to failure discriminator 120, where the failure discriminator 120 compares the stored data to the expected result and stores the result of the comparison to the failure memory 128 at a row address X3 and a column address Y3. Therefore, due to the latency of the DUT 124 the test result is stored at failure memory addresses X3 and Y3 instead of the failure addresses X1 and Y1.
FIG. 3 is a diagram showing the addressing of a failure memory and a memory device under test shown in FIG. 1. Referring to FIG. 3, data D1, D2, D3, and D4 stored in the DUT 124 is provided to the comparator 126 and compared with an expected value. When data D1 corresponding to the cell address X1 and Y1 is compared with the expected value, a test result T1, i.e., a result of the comparison, should be stored in the failure address X1 and Y1. Due to the latency of the DUT 124, however, the test result T1 is erroneously stored in a failure address X3 and Y3. When data D2 corresponding to the memory address X2 and Y2 is compared with an expected value and a test result T2 is stored in a failure address X4 and Y4. Similarly, when data D3 and D4 are read and compared with corresponding expected values, both of test results T3 and T4 are stored in the failure address X4 and Y4. The test result T2 stored in the failure memory 128, therefore, may be erased when the test result T3 is stored, and test result T3 may be erased when T4 is stored. This errant storage of test results may cause the redundancy algorithm to perform improperly.
One solution to overcome this problem is to delay accessing the DUT 124 the latency period. This solution, however, requires an additional testing time. A separate addressing approach is disclosed in Korea Patent No. 0199217, where an address generated from an address generator is divided into an address to a test memory and an address to a failure memory. This approach, however, however, does not allow independent addressing of a memory device under test and to a failure memory, and thus the may erroneously store failure test results.